Programmable Logic Device (CPLD)
● Capacity equivalent to 4000 programmable logic gates
● 48 I/O pins 6 dedicated inputs
● 144 registers
● High-speed global interconnects
● Input array fan-in is large, suitable for configuring high-speed counters, state machines, and address decoders with large fan-in
● Small logic blocks are suitable for building random logic circuits
● Encryption unit can prevent illegal data copying
● High-performance E2 PROM technology
● Maximum operating frequency of fmax=60MHZ
● Output delay of tpd=20ns
● Input and output compatible with TTL level
● Electrically erasable
● Non-volatile E2 PROM technology
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