CPLD

The capacity is equivalent to 4000 programmable logic gates

48 I/O pins and 6 dedicated inputs

144 registers

High-speed global interconnects

The input array has a large fan-in, which is suitable for high-speed counters, state machines, and address decoders configured as large fan-in

Logic blocks are smaller and suitable for building random logic circuits

The encryption unit prevents unauthorized data copying

High-performance E2 PROM technology

fmax = maximum operating frequency of 60MHZ

tpd=20ns output delay

The inputs and outputs are TTL level compatible

Electrically rewritable

Non-volatile E2 PROM technology