CLBs

6 Input Lookup Tables (LUTs)

Features with storage logic

It has the function of registers and shift registers

CMT

High-rate caching and low-jitter clock cabling schemes

Frequency synthesis and phase shifting

Low-jitter clock generation and jitter filtering

DSP Slice

25x18-bit multiplier and accumulator with complement function

Low-power pre-adder

Choice of pipelining, ALU and cascading

Block RAM

Dual-port 36Kb RAM block with up to 72-bit bit width

Built-in FIFO logic

Built-in selectable error correction circuit

Select IO interface technology

High-performance Select IO technology with DDR3 interface support

High-frequency decoupling capacitors can improve package integration

Numerically controlled impedance (DCI) active terminals support low power consumption and high rates

Flexible logical resources that support dynamic reconfigurable functionality

Low-Power Gigabit Transceivers

High-speed serial transceivers

Low-power mode optimization based on chip-to-chip connectivity

Secure Chip AES Bitstream Encryption

XADC (Analog-to-Digital Converter)

Dual 12-bit, 1MSPS sample-rate ADCs

On-chip or external references

On-chip temperature and voltage sensors

JTAG mode is supported

 PCIE3.0

Integrated PCIExpress® (PCIe) module, ×8 Gen3

Supports 2.5Gb/s, 5Gb/s, and 8Gb/s link speeds

It supports 1, 2, 4, and 8 channel connections

Supports 64-bit, 128-bit, and 256-bit user interfaces

1.0V core operating voltage

Compatible Type:XC7VX690T-2FFG1930I

Logical arrays（CLB）：693120

Block RAM(36Kbits)：1470

Maximum distributed RAM（Kbit）：10888

Package：BGA1930